//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "c:/cloudroom/releases/2014.09/shared/adobe/Iridas/IRIDASLIB/GPU/SecondaryPass4.cu", 1418102644, 4555
	.file	2 "c:\\cloudroom\\releases\\2014.09\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1418102788, 191626
.global .texref texture0_RECT;
.global .texref texture1_RECT;
// ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local has been demoted
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry ShaderKernel_SecondaryPass4(
	.param .u64 ShaderKernel_SecondaryPass4_param_0,
	.param .u32 ShaderKernel_SecondaryPass4_param_1,
	.param .u32 ShaderKernel_SecondaryPass4_param_2,
	.param .u32 ShaderKernel_SecondaryPass4_param_3,
	.param .u32 ShaderKernel_SecondaryPass4_param_4,
	.param .u64 ShaderKernel_SecondaryPass4_param_5,
	.param .u64 ShaderKernel_SecondaryPass4_param_6,
	.param .u64 ShaderKernel_SecondaryPass4_param_7
)
{
	.reg .pred 	%p<12>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<22>;
	.reg .f32 	%f<216>;
	.reg .s64 	%rd<35>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local[160];

	ld.param.u64 	%rd3, [ShaderKernel_SecondaryPass4_param_0];
	ld.param.u32 	%r4, [ShaderKernel_SecondaryPass4_param_1];
	ld.param.u32 	%r5, [ShaderKernel_SecondaryPass4_param_2];
	ld.param.u32 	%r6, [ShaderKernel_SecondaryPass4_param_3];
	ld.param.u32 	%r7, [ShaderKernel_SecondaryPass4_param_4];
	ld.param.u64 	%rd4, [ShaderKernel_SecondaryPass4_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	.loc 1 37 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	.loc 1 37 1
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	.loc 1 37 1
	@!%p3 bra 	BB0_15;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 37 1
	cvt.rn.f32.s32	%f35, %r2;
	add.ftz.f32 	%f1, %f35, 0f3F000000;
	cvt.rn.f32.s32	%f36, %r3;
	add.ftz.f32 	%f2, %f36, 0f3F000000;
	.loc 1 37 1
	setp.gt.u32	%p4, %r1, 9;
	@%p4 bra 	BB0_3;

	.loc 1 37 1
	mul.wide.u32 	%rd5, %r1, 16;
	mov.u64 	%rd6, ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local;
	add.s64 	%rd7, %rd6, %rd5;
	add.s64 	%rd8, %rd1, %rd5;
	ld.global.v4.f32 	{%f37, %f38, %f39, %f40}, [%rd8];
	st.shared.v4.f32 	[%rd7], {%f37, %f38, %f39, %f40};

BB0_3:
	.loc 1 37 1
	bar.sync 	0;
	.loc 1 37 111
	// inline asm
	tex.2d.v4.f32.f32 {%f45, %f46, %f47, %f48}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	.loc 1 37 1
	add.ftz.f32 	%f97, %f1, 0f00000000;
	add.ftz.f32 	%f56, %f2, 0fBF800000;
	.loc 1 37 111
	// inline asm
	tex.2d.v4.f32.f32 {%f51, %f52, %f53, %f54}, [texture0_RECT, {%f97, %f56}];
	// inline asm
	.loc 1 37 1
	add.ftz.f32 	%f62, %f2, 0fC0000000;
	.loc 1 37 111
	// inline asm
	tex.2d.v4.f32.f32 {%f57, %f58, %f59, %f60}, [texture0_RECT, {%f97, %f62}];
	// inline asm
	.loc 1 37 1
	add.ftz.f32 	%f68, %f2, 0fC0400000;
	.loc 1 37 111
	// inline asm
	tex.2d.v4.f32.f32 {%f63, %f64, %f65, %f66}, [texture0_RECT, {%f97, %f68}];
	// inline asm
	.loc 1 37 1
	add.ftz.f32 	%f74, %f2, 0fC0800000;
	.loc 1 37 119
	// inline asm
	tex.2d.v4.f32.f32 {%f69, %f70, %f71, %f72}, [texture0_RECT, {%f97, %f74}];
	// inline asm
	.loc 1 37 1
	ld.shared.v4.f32 	{%f105, %f106, %f107, %f108}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local+48];
	.loc 1 37 1
	mul.ftz.f32 	%f110, %f54, %f105;
	mul.ftz.f32 	%f112, %f60, %f106;
	mul.ftz.f32 	%f114, %f66, %f107;
	mul.ftz.f32 	%f116, %f72, %f108;
	.loc 1 37 1
	add.ftz.f32 	%f80, %f2, 0f3F800000;
	.loc 1 37 119
	// inline asm
	tex.2d.v4.f32.f32 {%f75, %f76, %f77, %f78}, [texture0_RECT, {%f97, %f80}];
	// inline asm
	.loc 1 37 1
	add.ftz.f32 	%f86, %f2, 0f40000000;
	.loc 1 37 119
	// inline asm
	tex.2d.v4.f32.f32 {%f81, %f82, %f83, %f84}, [texture0_RECT, {%f97, %f86}];
	// inline asm
	.loc 1 37 1
	add.ftz.f32 	%f92, %f2, 0f40400000;
	.loc 1 37 119
	// inline asm
	tex.2d.v4.f32.f32 {%f87, %f88, %f89, %f90}, [texture0_RECT, {%f97, %f92}];
	// inline asm
	.loc 1 37 1
	add.ftz.f32 	%f98, %f2, 0f40800000;
	.loc 1 37 119
	// inline asm
	tex.2d.v4.f32.f32 {%f93, %f94, %f95, %f96}, [texture0_RECT, {%f97, %f98}];
	// inline asm
	.loc 1 37 1
	fma.rn.ftz.f32 	%f117, %f78, %f105, %f110;
	fma.rn.ftz.f32 	%f118, %f84, %f106, %f112;
	fma.rn.ftz.f32 	%f119, %f90, %f107, %f114;
	fma.rn.ftz.f32 	%f120, %f96, %f108, %f116;
	.loc 1 37 1
	add.ftz.f32 	%f121, %f117, %f118;
	add.ftz.f32 	%f122, %f121, %f119;
	add.ftz.f32 	%f123, %f122, %f120;
	add.ftz.f32 	%f124, %f123, %f48;
	ld.shared.f32 	%f125, [ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local+76];
	mul.ftz.f32 	%f7, %f124, %f125;
	.loc 1 37 119
	// inline asm
	tex.2d.v4.f32.f32 {%f99, %f100, %f101, %f102}, [texture1_RECT, {%f1, %f2}];
	// inline asm
	.loc 1 37 1
	ld.shared.v4.f32 	{%f126, %f127, %f128, %f129}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local+112];
	.loc 1 37 1
	mul.ftz.f32 	%f130, %f46, %f127;
	fma.rn.ftz.f32 	%f131, %f47, %f126, %f130;
	fma.rn.ftz.f32 	%f132, %f45, %f128, %f131;
	.loc 1 37 1
	sub.ftz.f32 	%f133, %f47, %f132;
	sub.ftz.f32 	%f134, %f46, %f132;
	sub.ftz.f32 	%f135, %f45, %f132;
	.loc 1 37 1
	ld.shared.v4.f32 	{%f136, %f137, %f138, %f139}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local+128];
	.loc 1 37 1
	fma.rn.ftz.f32 	%f141, %f133, %f136, %f132;
	fma.rn.ftz.f32 	%f143, %f134, %f137, %f132;
	fma.rn.ftz.f32 	%f145, %f135, %f138, %f132;
	.loc 1 37 1
	ld.shared.v4.f32 	{%f146, %f147, %f148, %f149}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local];
	ld.shared.v4.f32 	{%f151, %f152, %f153, %f154}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local+32];
	.loc 1 37 1
	fma.rn.ftz.f32 	%f156, %f141, %f151, %f146;
	fma.rn.ftz.f32 	%f159, %f143, %f152, %f147;
	fma.rn.ftz.f32 	%f162, %f145, %f153, %f148;
	.loc 1 37 1
	setp.lt.ftz.f32	%p5, %f156, 0f00000000;
	selp.f32	%f13, 0fBF800000, 0f3F800000, %p5;
	setp.lt.ftz.f32	%p6, %f159, 0f00000000;
	selp.f32	%f14, 0fBF800000, 0f3F800000, %p6;
	setp.lt.ftz.f32	%p7, %f162, 0f00000000;
	selp.f32	%f15, 0fBF800000, 0f3F800000, %p7;
	.loc 2 2750 10
	abs.ftz.f32 	%f16, %f156;
	abs.ftz.f32 	%f17, %f159;
	abs.ftz.f32 	%f18, %f162;
	.loc 1 37 1
	ld.shared.f32 	%f19, [ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local+16];
	setp.gtu.ftz.f32	%p8, %f16, 0f00000000;
	@%p8 bra 	BB0_5;

	mov.f32 	%f213, 0f00000000;
	bra.uni 	BB0_6;

BB0_5:
	.loc 2 3600 10
	lg2.approx.ftz.f32 	%f164, %f16;
	mul.ftz.f32 	%f165, %f19, %f164;
	ex2.approx.ftz.f32 	%f213, %f165;

BB0_6:
	.loc 1 37 1
	ld.shared.f32 	%f22, [ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local+20];
	setp.gtu.ftz.f32	%p9, %f17, 0f00000000;
	@%p9 bra 	BB0_8;

	mov.f32 	%f214, 0f00000000;
	bra.uni 	BB0_9;

BB0_8:
	.loc 2 3600 10
	lg2.approx.ftz.f32 	%f167, %f17;
	mul.ftz.f32 	%f168, %f22, %f167;
	ex2.approx.ftz.f32 	%f214, %f168;

BB0_9:
	.loc 1 37 1
	ld.shared.f32 	%f25, [ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local+24];
	setp.gtu.ftz.f32	%p10, %f18, 0f00000000;
	@%p10 bra 	BB0_11;

	mov.f32 	%f215, 0f00000000;
	bra.uni 	BB0_12;

BB0_11:
	.loc 2 3600 10
	lg2.approx.ftz.f32 	%f170, %f18;
	mul.ftz.f32 	%f171, %f25, %f170;
	ex2.approx.ftz.f32 	%f215, %f171;

BB0_12:
	.loc 1 37 1
	mul.ftz.f32 	%f172, %f213, %f13;
	mul.ftz.f32 	%f173, %f214, %f14;
	.loc 1 37 1
	mul.ftz.f32 	%f174, %f173, %f127;
	fma.rn.ftz.f32 	%f175, %f172, %f126, %f174;
	.loc 1 37 1
	mul.ftz.f32 	%f176, %f215, %f15;
	.loc 1 37 1
	fma.rn.ftz.f32 	%f177, %f176, %f128, %f175;
	.loc 1 37 1
	sub.ftz.f32 	%f178, %f172, %f177;
	sub.ftz.f32 	%f179, %f173, %f177;
	sub.ftz.f32 	%f180, %f176, %f177;
	.loc 1 37 1
	ld.shared.v4.f32 	{%f181, %f182, %f183, %f184}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local+144];
	.loc 1 37 1
	fma.rn.ftz.f32 	%f186, %f178, %f181, %f177;
	fma.rn.ftz.f32 	%f188, %f179, %f182, %f177;
	fma.rn.ftz.f32 	%f190, %f180, %f183, %f177;
	.loc 1 37 1
	ld.shared.v4.f32 	{%f191, %f192, %f193, %f194}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local+96];
	ld.shared.v4.f32 	{%f196, %f197, %f198, %f199}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170283_639_non_const_p_local+80];
	.loc 1 37 1
	fma.rn.ftz.f32 	%f201, %f47, %f196, %f191;
	fma.rn.ftz.f32 	%f204, %f46, %f197, %f192;
	fma.rn.ftz.f32 	%f207, %f45, %f198, %f193;
	mov.f32 	%f208, 0f3F800000;
	.loc 1 37 1
	sub.ftz.f32 	%f209, %f208, %f7;
	mul.ftz.f32 	%f210, %f209, %f201;
	fma.rn.ftz.f32 	%f28, %f7, %f186, %f210;
	mul.ftz.f32 	%f211, %f209, %f204;
	fma.rn.ftz.f32 	%f29, %f7, %f188, %f211;
	mul.ftz.f32 	%f212, %f209, %f207;
	fma.rn.ftz.f32 	%f30, %f7, %f190, %f212;
	.loc 1 37 1
	mad.lo.s32 	%r21, %r3, %r4, %r2;
	.loc 1 37 1
	cvt.s64.s32	%rd2, %r21;
	.loc 1 37 1
	setp.eq.s32	%p11, %r5, 0;
	@%p11 bra 	BB0_14;

	cvta.to.global.u64 	%rd29, %rd3;
	.loc 1 37 1
	shl.b64 	%rd30, %rd2, 4;
	add.s64 	%rd31, %rd29, %rd30;
	st.global.v4.f32 	[%rd31], {%f30, %f29, %f28, %f102};
	bra.uni 	BB0_15;

BB0_14:
	cvta.to.global.u64 	%rd32, %rd3;
	.loc 1 37 1
	shl.b64 	%rd33, %rd2, 3;
	add.s64 	%rd34, %rd32, %rd33;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f30;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f29;
	mov.b16 	%rs2, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f28;
	mov.b16 	%rs3, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f102;
	mov.b16 	%rs4, %temp;
}
	.loc 1 37 241
	st.global.v4.u16 	[%rd34], {%rs1, %rs2, %rs3, %rs4};

BB0_15:
	.loc 1 37 2
	ret;
}


